Samsung Develops New Transistor for Below 10nm DRAM

Samsung has achieved a major breakthrough in memory technology. The company has introduced a new transistor for below 10nm DRAM that could shape the future of DRAM chips. This will allow the firm to make advanced memory nodes such as 0a and 0b DRAM.
Samsung reveals new technology for future 0a and 0b DRAM nodes
According to a report from TheElec, Samsung Electronics and the Samsung Advanced Institute of Technology (SAIT) announced a new memory technology at the IEEE International Electron Devices Meeting (IEDM) held in San Francisco. The technology in question is a high-temperature amorphous oxide semiconductor transistor for sub-10nm cell-on-periphery (CoP) vertical channel DRAM.
CoP is a cutting-edge DRAM architecture that stacks memory cells vertically on top of peripheral circuits. While this design improves memory density and efficiency, it also creates big problems. During the stacking process, temperatures can reach around 550 degrees Celsius, damaging the peripheral transistors beneath the memory cells.
Samsung has now addressed this issue thanks to amorphous indium gallium oxide (InGaO). The company found that a vertical channel transistor with a 100nm channel length can withstand the high-temperature process. Even after a 550-degree nitrogen heat treatment process, the transistor showed a threshold voltage change of less than 0.1 electron volts.
Furthermore, in high-temperature and high-voltage experiments, the threshold voltage shift was only -8 mV, suggesting a stable operating lifespan of more than 10 years. The company said it analyzed the material using molecular dynamics (MD) and density functional theory (DFT) simulations. It also noted that the transistor’s high thermal stability comes from its ability to suppress the movement of positive and negative ions at the interface between the channel and the electrodes.
It is worth noting that the technology is still at the research stage. Industry insiders say it will take time before the new transistor makes its way to commercial DRAM products. However, it could be used in future sub-10nm DRAM nodes (0a and 0b generations) as mentioned above.










